SOI Wafers

Lus piav qhia luv luv:

Lub SOI wafer yog cov qauv zoo li cov qhaub cij nrog peb txheej; Xws li cov txheej txheem saum toj kawg nkaus (duab txheej), nruab nrab ntawm cov pa oxygen faus (rau cov txheej txheem SiO2 insulating) thiab hauv qab substrate (silicon bulk). SOI wafers yog tsim los siv txoj kev SIMOX thiab wafer bonding tshuab, uas tso cai rau cov txheej txheem thinner thiab raug ntau dua, cov tuab tuab thiab qhov tsis xws luag.

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Product Detail

Khoom cim npe

SOI Wafers (1)

Daim ntawv thov teb

1. High-speed integrated circuit

2. Cov khoom siv microwave

3. Kub kub sib xyaw ua ke Circuit Court

4. Cov khoom siv fais fab

5. Tsawg zog hluav taws xob sib xyaw ua ke

6. MAS

7. Tsawg voltage integrated circuit

Yam khoom		Kev sib cav
Zuag qhia tag nrho	Wafer Txoj kab uas hla 晶圆尺寸 (mm)	50/75/100/125/150/200mm ± 25um
	Bow/Warp 翘曲度(	<10 awm
	Cov khoom 颗粒度(	0.3um <30 ua
	Flats / Notch 定位边/定位槽	Flat los yog Notch
	Ntug Exclusion 边缘去除 (mm)	/
Ntaus Txheej 器件层	Ntaus-txheej hom / Dopant 器件层掺杂类型	N-Type/P-Type B/P/Sb/As
	Ntaus-layer Orientation 器件层晶向	<1-0-0> / <1-1-1> / <1-1-0>
	Ntaus-txheej Thickness 器件层厚度 (um)	0.1 ~ 300 hli
	Ntaus-txheej Resistivity 器件层电阻率 (ohm •cm)	0.001 ~ 100,000 ohm-cm
	Device-layer Particles 器件层颗粒度(	<30ea@0.3
	Device Layer TTV 器件层TTV(	<10 awm
	Ntaus Txheej Txheej 器件层表面处理	Polished
BOX	faus Thermal Oxide Thickness 埋氧层厚度(um)	50nm (500Å) ~ 15um
Kov Txheej 衬底	Kov Wafer Hom / Dopant 衬底层类型	N-Type/P-Type B/P/Sb/As
	Handle Wafer Orientation 衬底晶向	<1-0-0> / <1-1-1> / <1-1-0>
	Kov Wafer Resistivity 衬底电阻率 (ohm •cm)	0.001 ~ 100,000 ohm-cm
	Kov Wafer Thickness 衬底厚度(um)	> 100 yam
	Handle Wafer tiav 衬底表面处理	Polished
SOI wafers ntawm lub hom phiaj specifications tuaj yeem kho raws li cov neeg siv khoom xav tau.